Please join OpenHW Group Staff and Members at the upcoming RISC-V Summit
OpenHW Group will participate at the Summit in Booth P1. Below please find a listing of our booth and RISC-V Summit program sessions.
CORE-V
Embedded World 2023
Heading to Embedded World 2023? Stop by the OpenHW Group & Eclipse Foundation booth Hall 4 – 554. OpenHW Group will be highlighting their CORE-V Family of Open Source RISC-V Cores for High Volume Production SoCs.
Security for all - OpenHW Group leads the charge towards a secure future
Security has become a critical issue for the entire IoT supply chain in recent years, as the number of connected devices continues to grow and our reliance on them increases. With more devices connected to the internet, the potential for security breaches and data theft also increases.
OpenHWTV S1E6 webinar recording on Formal Verification for the CORE-V CVE4 now available on-demand
Watch OpenHW Group's latest webinar, the final episode of 2020, providing a Knowledge Boost into Formal Verification for the CORE-V CVE4. Held on November 20, the webinar episode, is available to watch on-demand.
Register for OpenHW TV Episode 6 focusing on Formal Verification for the CORE-V CVE4
Be sure to register for the next episode of OpenHW TV next Thursday 19th November @ 11am EST / 8am PST / 4pm BST for a deep dive into Formal Verification for the CORE-V CVE4. As always, your questions are answered live by our experts which will include Sven Beyer at OneSpin, Ashish Darbari from Axiomise and Mike Thompson from OpenHW Group. Register now: https://bit.ly/38C7hku
OpenHW TV Episode 5 now available on-demand
We live-streamed a fifth episode of OpenHW TV on Thursday 29 October. Guest presenters from Axiomise, EM Microelectronic, Imperas, Metrics, OneSpin and Silicon Labs all participated.
RISC-V Global Forum
Together with members Imperas and Metrics, we are gold sponsors of the RISC-V Global Forum. Register for our presentation on Thursday September 3 at 1:20pm Pacific Time on "CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores." This talk provides details of the CORE-V verification test bench, an open-source 'step & compare' System Verilog/UVM environment built by our ecosystem leveraging the Imperas RISC-V golden reference model and the Metrics Cloud-based EDA platform.
OpenHW TV Episode 3 register now - CORE-V SW and HW in the FPGA environment
The next episode of OpenHW TV will stream live on Thursday August 20 at 11am EST / 8am PST / 4pm BST.
REGISTER HERE: https://bit.ly/2DJY4JP
OpenHW TV S1E02 - The CORE-V family of RISC-V cores
This episode looks at highlights of the OpenHW Group CORE-V family of RISC-V cores, focusing on the CVE4 and CVA6 cores, an update of their current status within the OpenHW Group and discussing how new contributors can participate in the development of these cores.
Following the overview there will be a live Q&A session with our panellists.
OpenHW TV Episode 2 register now - The CORE-V family of RISC-V cores
The next episode of OpenHW TV will stream live on Thursday 16th July at 11am EST / 8am PST / 4pm BST.
REGISTER HERE: https://bit.ly/2ZvxsmZ