Beyond the basics: Elevating Eclipse ThreadX to a first-class RTOS for RISC-V

As the RISC-V instruction set architecture (ISA) transitions from an academic platform to an increasingly large portion of industrial applications, the embedded and IoT software ecosystem faces a critical requirement: the availability of proven, safety-certified real-time operating systems (RTOS). ThreadX, in its various forms, has long served as a foundational component of the global embedded industry. With a legacy spanning back to 1997, today ThreadX represents a unique blend of commercial maturity and open source versatility and speed.

However, the rapid adoption of RISC-V posed a notable challenge for ThreadX’s core contributors and developers. While early ports for the RISC-V ISA existed, they often lacked the robust, commercial quality required for high-performance adoption. This challenge was particularly concerning for 64-bit implementations. To address this, the ThreadX Senior Project Lead Frédéric Desbiens and Akif Ejaz, Sr. Systems/Firmware Software Engineer at 10x Engineers, launched a joint effort to bring first-class RISC-V support to ThreadX RTOS in the latest release and recently presented their work at the 2026 RISC-V Summit Europe in Bologna, Italy.

Modernising ThreadX for RISC-V

The effort to adapt ThreadX for RISC-V required a deep dive into the architectural intricacies of the RISC-V ISA. The collaboration between 10xEngineers and the ThreadX project team focused on resolving the complexities inherent in porting core components to both RV32 and RV64 environments.

A primary focus was the optimisation of functions for the RISC-V privileged architecture. This included a rigorous redesign of context switching, interrupt nesting, and timer management. On RISC-V, these operations interact directly with the privileged hardware registers, requiring extreme precision to maintain real-time guarantees. The team found that some register saving, which is often employed in preliminary ports, was insufficient for modern, high-performance extensions like floating-point and vector units. Consequently, the project implemented systematic procedures that ensure integrity across complex execution states.

Additionally, the standardisation of existing RISC-V board support packages (BSPs) was improved. By refactoring these packages, the team lowered the effort needed for the ThreadX community to support a diverse range of hardware. The contributions also moved ThreadX away from hardcoded, platform-specific profiles that previously hampered some cross-platform portability. 

Practical enablement: From virtual prototyping to physical hardware

Bridging the gap between virtual prototyping and physical deployment was facilitated by the integration of QEMU into the project’s continuous integration (CI) pipeline. This integration allowed the project to run automated regression test suites on QEMU for both RV32 and RV64 architectures. Besides this, added RISC-V board “BananaPI BPI-F3” BSP in ThreadX, which has SpacemiT K1 SoC. This testing regime proved invaluable for catching latent, platform-specific bugs such as a missing MIE bit during mstatus setup that would have been nearly impossible to isolate on bare metal. This "test-first" approach ensures that incoming RISC-V contributions maintain the high standards required for a safety-certified application, allowing the project to evolve without regressing in stability. 

The recent v6.5.1 release in June 2026 marked a pivotal milestone for RISC-V support in ThreadX by integrating contributions which added RISC-V Vector Extension (RVV) support for 64-bit architectures and contributed a new 32-bit port for the OpenHW CVA6 application-class processor. Yet, the roadmap for ThreadX is significantly more ambitious, establishing ThreadX as a "RISC-V-first" operating system.

The power of collaboration across Eclipse Foundation Working Groups

The success of ThreadX in the RISC-V space is deeply influenced by the collaborative, vendor-neutral governance model of the Eclipse Foundation. When paired with open hardware like the OpenHW Foundation’s open source processor cores, ThreadX enables a fully transparent, auditable, trustable, and portable stack.

The involvement of the OpenHW Foundation highlights ThreadX’s broader strategy to create an ecosystem where software and hardware co-design ensures that safety, security, and performance are built into the very fabric of the system. This model provides an alternative to the closed, opaque development processes often found in the proprietary embedded market, offering developers the reliability of a safety certified RTOS combined with the flexibility and speed of open source ecosystems.

A cornerstone for future embedded systems

As the RISC-V ecosystem continues to mature, ThreadX is positioned as more than just a standalone kernel. By addressing the architectural challenges of the RISC-V ISA and committing to a quarterly, transparent, automated development lifecycle, the project has solidified its role as a cornerstone of the modern open-source embedded landscape.

For the future of software-defined vehicles and the broader embedded and IoT landscape, the transition to a RISC-V first ecosystem is inevitable. Through the continued integration of features like PMP, SMP, additional hardware support, and hypervisor-level virtualisation, ThreadX is prepared to support the next generation of embedded innovation, ensuring that the promise of open hardware is matched by the performance and security of open-source software.

To get involved with the ThreadX project, explore the Eclipse ThreadX repository or reach out to learn more about the ThreadX Alliance. You can learn more about the evolution of RISC-V support for ThreadX by watching Frédéric Desbiens present the "Beyond the Basics poster at the RISC-V Summit Europe 2026 or explore the poster in depth below.