Be sure to register for the next episode of OpenHW TV next Thursday 19th November @ 11am EST / 8am PST / 4pm BST for a deep dive into Formal Verification for the CORE-V CVE4. As always, your questions are answered live by our experts which will include Sven Beyer at OneSpin, Ashish Darbari from Axiomise and Mike Thompson from OpenHW Group. Register now: https://bit.ly/38C7hku
We live-streamed a fifth episode of OpenHW TV on Thursday 29 October. Guest presenters from Axiomise, EM Microelectronic, Imperas, Metrics, OneSpin and Silicon Labs all participated.
Together with members Imperas and Metrics, we are gold sponsors of the RISC-V Global Forum. Register for our presentation on Thursday September 3 at 1:20pm Pacific Time on "CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores." This talk provides details of the CORE-V verification test bench, an open-source 'step & compare' System Verilog/UVM environment built by our ecosystem leveraging the Imperas RISC-V golden reference model and the Metrics Cloud-based EDA platform.
The next episode of OpenHW TV will stream live on Thursday August 20 at 11am EST / 8am PST / 4pm BST.
REGISTER HERE: https://bit.ly/2DJY4JP
This episode looks at highlights of the OpenHW Group CORE-V family of RISC-V cores, focusing on the CVE4 and CVA6 cores, an update of their current status within the OpenHW Group and discussing how new contributors can participate in the development of these cores.
Following the overview there will be a live Q&A session with our panellists.
The next episode of OpenHW TV will stream live on Thursday 16th July at 11am EST / 8am PST / 4pm BST.
REGISTER HERE: https://bit.ly/2ZvxsmZ
We’re excited to announce our latest initiative to help us amplify the value of open source processor IP – OpenHWTV. It’s a series of online events that look at the barriers to adoption of opensource IP and in each episode, we delve a little deeper into different areas with help from our 45+ members.
