2024 Siemens EDA Forum Shanghai
The 2024 Siemens EDA Forum will be held in Shanghai on 19 September 2024. OpenHW will showcase our latest open source, industrial grade RISC-V Cores and how they are working flawlessness with Siemens EDA Tools.
#SystemVerilog
COSCUP 2024 - Open Source Inspired Hardware (and their happy friends)
At the COSCUP 2024 our OpenHW Group Flo will be onside and present at Open Source Inspired Hardware (and their happy friends) for TR611 the topic "RISC-V Cores in industrial quality and Open Source" make sure to join COSCUP, hang out, talk with others and bring everything forward together! Free admission, but feel free to take the survey of the Homepage to support the organizers!
Verification Futures Conference 2024 Austin - Accelerate your adoption of RISC-V with CORE-V-VERIF
Mike Thompson will speak about how to Accelerate your adoption of RISC-V with CORE-V-VERIF.
CORE-V-VERIF is an open source project supported by the OpenHW Group. Its goal is to provide an open-source environment and workflow that can be deployed into any RISC-V processor core. Since December 2020, OpenHW Group members have successfully used CORE-V-VERIF for end-to-end verification of more than six RISC-V cores.