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  4. OpenHW TV Episode 3 register now - CORE-V SW and HW in the FPGA environment

OpenHW TV Episode 3 register now - CORE-V SW and HW in the FPGA environment

Tuesday, August 11, 2020 - 09:43

The next episode of OpenHW TV will stream live on Thursday August 20 at 11am EST / 8am PST / 4pm BST.

REGISTER HERE: https://bit.ly/2DJY4JP

In this episode we give a detailed update of work in our HW and SW Task Groups, as well as featuring guest member Ashling. You can hear about the work of the SW and HW Task Groups to date including an outlook to future roadmaps, a detailed look at the GNU tool chain work and an overview of the Ashling RiscFree IDE with a demo of the debug interface to the HW Task Group board. 

Speakers on the live panel for our Q&A will be:

Jeremy Bennett - CEO at Embecosm and Chair of the Software Task Group at OpenHW Group.

Hugh Pollitt-Smith - Senior Engineer, System Design and Embedded Systems Group Lead at CMC Microsystems / Co-chair of the Hardware Task Group and Co-chair of the University Outreach Task Group at OpenHW Group. 

Roisin O'Keeffe - VP Business Development at Ashling

 

Tags: 
OpenHW Group
CORE-V
RISC-V
open source processor cores
FPGA
IDE

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