RISC-V

The 2024 Siemens EDA Forum will be held in Shanghai on 19 September 2024. OpenHW will showcase our latest open source, industrial grade RISC-V Cores and how they are working flawlessness with Siemens EDA Tools.

At the COSCUP 2024 our OpenHW Group Flo will be onside and present at Open Source Inspired Hardware (and their happy friends) for TR611 the topic "RISC-V Cores in industrial quality and Open Source" make sure to join COSCUP, hang out, talk with others and bring everything forward together! Free admission, but feel free to take the survey of the Homepage to support the organizers!

The OpenHW Group is exhibiting at the RISC-V Summit China! Make sure to talk to us about industrial grade, open source RISC-V Cores! Listen to Flo, who will present in person, give a talk and we have a table.

Mike Thompson will speak about how to Accelerate your adoption of RISC-V with CORE-V-VERIF.

CORE-V-VERIF is an open source project supported by the OpenHW Group. Its goal is to provide an open-source environment and workflow that can be deployed into any RISC-V processor core. Since December 2020, OpenHW Group members have successfully used CORE-V-VERIF for end-to-end verification of more than six RISC-V cores.

The OpenHW Group is exhibiting at the RISC-V Summit Europe!
Make sure to talk to us about industrial grad, open Source RISC-V Cores!
Listen to the program hearing Members talk about CVA6, CVE4 and other IP we provide!

www.OpenHWgroup.org

Can you design a commercial chip and ship hundreds of millions of units? The OpenHW Group is dedicated to curating and maintaining industrial-quality, open-source RISC-V IP with its members. This includes full verification and documentation under a permissive license. OpenHW Group's RISC-V IP has already been used in many different commercial applications and is ideally suited for custom extensions or modifications. However, it also works effectively off-the-shelf.