RISC-V

OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing

Tuesday, November 7, 2023 - 11:41 by Olivier Goulet

Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project. The platform is an open-source FPGA-based software development and testing environment for RISC-V processors designed to provide a vendor-neutral environment for RISC-V software CI and testing that keeps pace with RISC-V standards.

Embedded World 2023

Wednesday, March 8, 2023 - 09:54 by Olivier Goulet

Heading to Embedded World 2023? Stop by the OpenHW Group & Eclipse Foundation booth Hall 4 – 554. OpenHW Group will be highlighting their CORE-V Family of Open Source RISC-V Cores for High Volume Production SoCs.

New episode of OpenHW TV (Season 2) available to watch

Thursday, January 28, 2021 - 16:58 by Nayl DSouza

The opening episode of 2021 features an interview between embedded.com editor-in-chief Nitin Dahad and OpenHW Group President and CEO Rick O'Connor. They discuss the latest milestones of the OpenHW Group, the roadmap for the organization, and the key drivers for growth of open source processor development, among other topics.
 

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<span>New episode of OpenHW TV (Season 2)  available to watch</span>
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RISC-V Global Forum

Together with members Imperas and Metrics, we are gold sponsors of the RISC-V Global Forum. Register for our presentation on Thursday September 3 at 1:20pm Pacific Time on "CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores." This talk provides details of the CORE-V verification test bench, an open-source 'step & compare' System Verilog/UVM environment built by our ecosystem leveraging the Imperas RISC-V golden reference model and the Metrics Cloud-based EDA platform.

OpenHW TV Episode 1 now available on-demand

Monday, June 29, 2020 - 09:06 by Andrea Barnard
We live-streamed a world-class first episode of OpenHW TV on 18th June and even exceeded our registration numbers, as guest presenters from Metrics and Imperas highlighted the open source CORE-V processor IP design verification plan.
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<span>OpenHW TV Episode 1 now available on-demand</span>
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