OpenHW Group gears up for RISC-V Summit (8 – 10 December 2020)
We're looking forward to meeting with old and new industry peers and friends at the RISC-V Summit. Below, we list the keynote presentations and key discussions that the OpenHW Group is directly involved with. To register for the event, use this link and use the code ‘OPENHW’ to apply a 25% discount: https://bit.ly/3om7kWa
The event may be virtual, but we're still very happy to meet with you on a 1:2:1 personal basis and the team has especially set aside time to do this. Contact us to arrange a meeting time.
Don't forget there's also a chance to meet with five OpenHW Group members at the Summit at their respective booths. And do remember to stop by and see CORE-V Verification and CORE-V MCU FPGA & SoC related demonstrations.
Tuesday, 8 December
1:50pm - 2:00pm PST (10 mins)
Tech Talk with OpenHW Group: CORE-V Verification Test Bench
We will briefly introduce the OpenHW Group and its top-down approach to verification.
With Mike Thompson - Director of Verification Engineering, OpenHW Group
3:30pm - 3:50pm PST (20 mins)
Hardware Cores/SoCs
An overview of OpenHW's CORE-V MCU SoC, Open Source, 22nm Embedded MCU with eFPGA
With Florian Zaruba - Director of Engineering, HW & SW Task Groups, OpenHW Group
4:00pm - 4:30pm PST (30 mins)
LIVE Q&A Forum with Speakers: Room B
Florian Zaruba is joined by:
Bill McSpadden (Seagate), Dennis Griffith (Lauterbach), Art Swift (Esperanto), Charlie Su (Andes), Manuel Offenberg (Seagate), Atish Patra (Western Digital), Tu Dang (Western Digital), and Lee Moore (Imperas).
Wednesday, 9 December 2020
9:15am - 9:30am PST (15 mins)
Keynote: CORE-V: Industrial Grade Open Source RISC-V Cores
An overview of the CORE-V family project and its verification using CORE-V-VERIF, a silicon-proven, industrial-grade functional verification platform.
With Rick O'Connor - President & CEO, OpenHW Group
9:30am - 10:00am PST (30 mins)
Keynote: Is RISC-V Verification Ecosystem Ready for the Coming Innovation Tsunami?
The processor IP business model was based on the leveraged of one-size-fits all over many projects to offset the upfront investment. If the innovation with RISC-V increases the verification work on each design does this affect the bandwidth across the industry to support this shift in the verification responsibility?
Mike Thompson is joined by:
Ann Mutschler - Executive Editor/EDA, Semiconductor Engineering
Simon Davidmann - President & CEO, Imperas Software Ltd
Steve Richmond - Design Verification Manager for the Central R&D Division, Silicon Labs
Nasr Ullah - Senior Director, Performance Architecture, SiFive
10:30am - 11:00am PST (30 mins)
LIVE Q&A Forum with the Keynote Speakers
Meet the Speakers: Room A
Rick and Mike are joined by Ann Mutschler (Semiconductor Engineering), Simon Davidmann (Imperas), Steve Richmond (Silicon Labs), Nasr Ullah (SiFive), Krste Asanovic (UC Berkeley | SiFive), Nitin Dahad (embedded.com), David Patterson (RISC-V), and Chris Lattner (SiFive).
Thursday, 10 December 2020
Tutorial: 12:00pm - 1:00pm PST (60 mins)
CORE-V-VERIF, an Industrial-Grade Verification Platform for RISC-V cores
An hour-long tutorial session which delves into the details of the simulation and formal verification applied to the CV32E40P project.
Mike Thompson is joined by:
Sven Beyer - Product Manager Design Verification,OneSpin Solutions
Steve Richmond - Design Verification Manager for the Central R&D Division, Silicon Labs
1:15pm - 2:00pm PST (45 mins)
Meet the Speakers: Room A – LIVE Q&A Forum with Speakers
Mike, Sven and Steve are joined by:
Simon Davidmann (Imperas), Lee Moore (Imperas), Barry Spinney (Nvidia), Jamey Hicks (Accelerated Tech), Stephano Cetola (Linux), Mark Himelstein (RISC-V International), and Jeffrey Osier-Mixon (RISC-V International and Linux), among others.
Register now: https://bit.ly/3om7kWa
When registering, don't forget to use the code ‘OPENHW’ for a 25% discount.
Sixty Group members/partners and counting
It has been just over a year since the OpenHW Group became operational. Today, we have attracted over 60 members and partners, far exceeding our initial goal. Organizations from all over the world continue to join us, strengthening our ecosystem and helping to facilitate the collaborative development of open-source cores, IP, tools and software. We value every member that's joined our community – all supporting us in our mission to promote the development of high-quality open-source cores and related IP that the semiconductor industry can trust.
OpenHWTV
We aired our first episode of OpenHW TV in June 2020. This was a new project to amplify the value of open source processor IP. Since then, we have recorded six live episodes during the year which are all available for on-demand viewing. Hundreds of participants have attended the live broadcasts, asking questions to our panelists made up of Task Group Chairs and guest presenters from member organizations.
Our next episode in a brand new series in 2021 is scheduled to air on 21 January.
All episodes available from OpenHW TV channel:
https://bit.ly/2VAnD5C