2024 Siemens EDA Forum Shanghai
The 2024 Siemens EDA Forum will be held in Shanghai on 19 September 2024. OpenHW will showcase our latest open source, industrial grade RISC-V Cores and how they are working flawlessness with Siemens EDA Tools.
#RISC-V
How to leverage/use Open Source RISC-V IP in Industry
RISC-V Europe 2024 Summit recap "How to leverage Open Source in Industry", by Jean-Roch Coulon, Thales (Thales Silicon Security).
COSCUP 2024 - Open Source Inspired Hardware (and their happy friends)
At the COSCUP 2024 our OpenHW Group Flo will be onside and present at Open Source Inspired Hardware (and their happy friends) for TR611 the topic "RISC-V Cores in industrial quality and Open Source" make sure to join COSCUP, hang out, talk with others and bring everything forward together! Free admission, but feel free to take the survey of the Homepage to support the organizers!
RISC-V Summit China 2024
The OpenHW Group is exhibiting at the RISC-V Summit China! Make sure to talk to us about industrial grade, open source RISC-V Cores! Listen to Flo, who will present in person, give a talk and we have a table.
Verification Futures Conference 2024 Austin - Accelerate your adoption of RISC-V with CORE-V-VERIF
Mike Thompson will speak about how to Accelerate your adoption of RISC-V with CORE-V-VERIF.
CORE-V-VERIF is an open source project supported by the OpenHW Group. Its goal is to provide an open-source environment and workflow that can be deployed into any RISC-V processor core. Since December 2020, OpenHW Group members have successfully used CORE-V-VERIF for end-to-end verification of more than six RISC-V cores.
OpenHW Group member Bluespec updates its free RISC-V tool with CV32e40p
Bluespec, Inc. just released an updated version of its RISC-V Explorer, a free tool for quickly and accurately evaluating RISC-V open source cores. The new release adds the OpenHW Group 4-stage CV32E40P core.
CORE-V CVE4 Functional RTL Freeze Milestone - register for OpenHW TV Episode 5
Back in June, the first episode of OpenHW TV looked at the CORE-V Verification Test Bench and our open-source RISC-V processor IP design verification plan. Just 4 months on and OpenHW Group is approaching the Functional RTL Freeze milestone for the CVE4.